Can you please send your PCB123 file to support@susntone.com so we can take a look of your symbol and footprint?

Yes, you can create solder mask opening by adding a filled polygon on the solder mask layer. Please note that solder mask layer is in negative polarity, so anything you draw on that layer, will have no solder mask.

For some user trying to install PCB123 on windows 8 PC, it might fail due to writing permission to some folders. Solution: Make sure you are the Admin of this PC, Make sure you are setting the right permission to the C:\Users\XXXXX\AppData\Local\Temp folder, and right click> properties> security> fu...

The new display driver for Surface Pro will casue PCB123 to crash. The program starts up fine, but when you try to open a file or create a new file, the program crashes. The work around will be revert back to the older May 2012 driver for the dispaly. To fix it, please go to your device manager> Exp...

You can change the schematic page size by right click on the schematic page and select "Set Page Size" Then you will see the page size options:

For some users that want to have different width for a trace on two different layers of the board connected by a VIA. You can not adjust the width for one trace going through a VIA to another layer. The only work around is use the add pin tool to add a pin to act as your VIA.

You can order Silver(RoHs) board on our PCBexpress Quickturn service and Full Feature service at no extra cost:

PCBexpress quickturn service: Full Feature service:

There is a bug in the PCB123. Pin name is different between the schematic symbol and footprint. You can work around this by selecting the part from the layout side and add it to your design. This way it will not give you error message, but will give you a different symbol. The cause of the this erro...

For the current version of PCB123 (After version 4.1.16.0), different filled polygon will be blend together if they are overlap. The work around for this right now, is to separate your filled copper pour into smaller sections, and then move them together like the sample below:

This is a consequence of a bug in PCB123 that is encountered when a pin is connected to a net on the schematic that is marked as “Do Not Optimize” in the layout’s “Edit Properties/Edit Nets” dialog. When the “Do Not Optimize” flag is set on a net, PCB123 will actively attempt to not modify a net’s r...