Removing Thermal Reliefs at Vias

Here you can find discussions pertaining to finding or creating Symbols and package footprints. Anything to do with Schematic or layout parts will be placed in this discussion.

Moderator: Sunstone Moderators

Removing Thermal Reliefs at Vias

Postby Ron » Mon May 14, 2012 9:30 am

In my design, I am not using through hole parts, and I'd like to remove the thermal reliefs shown at the connections of Plane Layers (or Solder Pours)and Vias. Is this just specified in a Readme file attached with the .123 file, or can I reflect this in the tool? Thanks
Posts: 1
Joined: Tue Sep 20, 2011 12:00 am

Re:Removing Thermal Reliefs at Vias

Postby Sal Hernandez » Mon May 14, 2012 9:30 am

If you have assigned your inner layers as planes you do not have any control over the thermal reliefs that are automatically generated. If you need the thermal reliefs removed you will need to add a note to your order and you will also need to order through the PCB Full Feature.

I would suggest using a filled polygon in place of a plane. When a via connects to a filled polygon you get a connection without a thermal relief. Only component through holes and pins placed using the add pin tool are thermally relieved when connected to a filled polygon.

Please contact customer support if you have any questions. 1-800-228-8198

Sal Hernandez
Software Support Engineer I
Sunstone Circuits
13626 S. Freeman Road
Mulino, OR 97042
Phone: 503-829-9108 x226
Fax: 503-829-5482
User avatar
Sal Hernandez
Posts: 396
Joined: Wed Jul 06, 2011 12:00 am

Re:Removing Thermal Reliefs at Vias

Postby Linda_I » Mon May 14, 2012 9:30 am

Another way to avoid thermal relief on inner layers is to: 1. Use area fills, not a plane layer 2. Run a fat trace from a pin, and wind it so it covers the thermal relief. The dangling end of the fat trace may come up as an error in DRC, but is ok 3. You can add thermal pins into large surface mount pads. Just select the pin Doughnut, and place pins in the pad 4. Right click on each thermal pin, and assign it to the same net as the pad. 5. Run fat traces over thermal releif. DRC might complain, but it works. The tool seems to fight putting the trace exactly where I want it, but it sometimes requires outsmarting the tool
Capture.JPG (19.5 KiB) Viewed 2590 times
Posts: 1
Joined: Tue Jan 24, 2012 1:00 am

Return to Schematic and Layout Parts (Libraries)

Who is online

Users browsing this forum: No registered users and 0 guests